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SN74LS251 8-Input Multiplexer with 3-State Outputs
The TTL/MSI SN74LS251 is a high speed 8-Input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS251 can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided.
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* * * * *
Schottky Process for High Speed Multifunction Capability On-Chip Select Logic Decoding Inverting and Non-Inverting 3-State Outputs Input Clamp Diodes Limit High Speed Termination Effects
LOW POWER SCHOTTKY
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current - High Output Current - Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 - 2.6 24 Unit V C mA mA
16 1
PLASTIC N SUFFIX CASE 648
16 1
SOIC D SUFFIX CASE 751B
ORDERING INFORMATION
Device SN74LS251N SN74LS251D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel
(c) Semiconductor Components Industries, LLC, 1999
1
December, 1999 - Rev. 6
Publication Order Number: SN74LS251/D
SN74LS251
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 I4 15 I5 14 I6 13 I7 12 S0 11 S1 10 S2 9
1 I3
2 I2
3 I1
4 I0
5 Z
6 Z
7 E0
8 GND
LOADING (Note a) PIN NAMES S0 - S2 E0 I0 - I7 Z Z Select Inputs Output Enable (Active LOW) Inputs Multiplexer Inputs Multiplexer Output Complementary Multiplexer Output HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. 65 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 U.L. 15 U.L.
NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOGIC DIAGRAM
I0 S2 S1 S0 E1
9 10 11 7 4
I1
3
I2
2
I3
1
I4
15
I5
14
I6
13
I7
12
VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Z
5
6
Z
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SN74LS251
FUNCTIONAL DESCRIPTION
The LS251 is a logical implementation of a single pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both assertion and negation outputs are provided. The Output Enable input (EO) is active LOW. When it is activated, the logic function provided at the output is:
Z = EO (I0 S0 S1 S2 + I1 S0 S1 S2 + I2 S0 S1 Z = E O S 2 + I 3 S 0 S 1 S 2 + I4 S 0 S 1 S 2 + I5 S 0 Z = EO S1 S2 + I6 S0 S1 S2 + I7 S0 S1 S2).
When the Output Enable is HIGH, both outputs are in the high impedance (high Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. When the outputs of the 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active LOW portion of the enable voltage.
TRUTH TABLE
E0 H L L L L L L L L L L L L L L L L S2 X L L L L L L L L H H H H H H H H S1 X L L L L H H H H L L L L H H H H S0 X L L H H L L H H L L H H L L H H I0 X L H X X X X X X X X X X X X X X I1 X X X L H X X X X X X X X X X X X I2 X X X X X L H X X X X X X X X X X I3 X X X X X X X L H X X X X X X X X I4 X X X X X X X X X L H X X X X X X I5 X X X X X X X X X X X L H X X X X I6 X X X X X X X X X X X X X L H X X I7 X X X X X X X X X X X X X X X L H Z (Z) H L H L H L H L H L H L H L H L Z (Z) L H L H L H L H L H L H L H L H
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care (Z) = High impedance (Off)
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SN74LS251
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.4 - 0.65 3.1 0.25 VO OL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 0.35 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current 12 mA - 30 - 0.4 - 130 10 0.5 20 - 20 20 V A A A mA mA mA mA IOL = 24 mA 0.4 Min 2.0 0.8 - 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 12 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
VCC = MAX, VOUT = 2.7 V VCC = MAX, VOUT = 0.4 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX, VE = 0 V VCC = MAX, VE = 4.5 V
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)
Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ Parameter Propagation Delay, Select to Z Output Propagation Delay, Select to Z Output Propagation Delay, Data to Z Output Propagation Delay, Data to Z Output Output Enable Time to Z Output Output Enable Time to Z Output Output Disable Time to Z Output Output Disable Time to Z Output Min Typ 20 21 29 28 10 9.0 17 18 17 24 30 26 37 15 30 15 Max 33 33 45 45 15 15 28 28 27 40 45 40 55 25 45 25 Unit ns ns ns ns ns ns ns ns Figure 1 Figure 2 Figure 1 Figures 2 Figures 4, 5 Figures 3, 5 Figures 3, 5 Figures 4, 5 CL = 5.0 pF, RL = 667 k CL = 15 pF, RL = 2.0 k Test Conditions
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SN74LS251
3-STATE AC WAVEFORMS
VIN
1.3 V tPLH
1.3 V tPHL 1.3 V
VIN
1.3 V tPHL
1.3 V tPLH 1.3 V
VOUT
1.3 V
VOUT
1.3 V
Figure 1.
Figure 2.
VE tPZL VOUT
1.3 V
1.3 V tPLZ
VE tPZH 1.3 V VOL VOUT
1.3 V tPHZ 1.3 V
1.3 V VOH 1.3 V 0.5 V
1.3 V 0.5 V
Figure 3.
0.5 V
Figure 4.
AC LOAD CIRCUIT
VCC
SWITCH POSITIONS
RL SYMBOL tPZH tPZL tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed
SW1
TO OUTPUT UNDER TEST
5 k CL* SW2
* Includes Jig and Probe Capacitance.
Figure 5.
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SN74LS251
PACKAGE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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SN74LS251
PACKAGE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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SN74LS251
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PUBLICATION ORDERING INFORMATION
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SN74LS251/D

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